How does Verilog implement low-power designs?
tempo di aggiornamento: 2021-07-20 11:24:22
Do the first chip should be concerned about the chip's PPA (Performance, Power, Area), this shallow part of the discussion, the second P, Power power consumption, how to achieve low-power design in RTL design, for mobile devices range is very important, do not let your chip increase power consumption in vain.
Data path register beat
Data register beat with vld, without adding reset logic, which will save the wiring area of the register reset circuit, and the tool will automatically insert the clock gating to the register, but also to achieve the effect of reducing power consumption.
As for the register does not reset, some friends just learning may feel some refreshing cognition, how can the register does not reset, not reset is not x-state, the system is not disorderly. Yes, the register is not reset will produce x-state, but here we are talking about the data path, the control path of all the signals are necessary with reset logic. Data path because here is with vld for beat, just make sure that when you use it, it is not x-state on the line. The control path signals control the operation of the system, there is an x-state, it is bound to hang. And the data pathway just need to ensure that in the vld of the valid, that is, I step on this data when it is correct on the line, regardless of whether it is x-state or other invalid data.
Of course, if the data has as a judgment logic for control, then this data must be reset.
Code example, timing logic can omit the else, the register default hold, the combination logic must write else. vld is a pulse will kick this data directly into this register storage, before the next kick comes, this register will hold this data.
Manual insertion of clock gating
Manually inserted clock gating automatically turns off the clock of some modules depending on the control scenario, leaving the control channel to be turned off by the software. This can effectively reduce dynamic power consumption.
For example, if an arithmetic circuit is configured to work with four identical computational modules at the same time, the least case requires only one module to work, and then the clocks of the other three modules can be turned off depending on the configuration to reduce dynamic power consumption.
Power down of the entire Top module
The entire secondary Top module is powered down to hibernate, and all data to be saved is written to memory after power down, and then re-written back to hardware when the next module is woken up and powered on. the RAM in the ASIC can generate its own function of whether it needs to be powered down to save data, and the RAM for specialized storage that is not needed is also powered down together.
The data registers that need to be used and saved are less and can be extended from the module to interface to the top level for software to read away and then configured back to the module via software configuration registers when the module wakes up for power-up startup next time. This is the low-power mode.
Static power consumption and dynamic power consumption
Static power consumption as long as the circuit power supply, unless power-down hibernation, it can not be avoided, dynamic power consumption as long as there is a high and low level switching. In rtl design, good code style can also reduce dynamic power consumption, multipliers, adders and other arithmetic units, by reducing the combinational logic flip-flop, thus reducing the effect of dynamic power consumption.
Input to output, the value of the a and b side of the combinational logic remains the same, there is no level flip, so there will be no dynamic power consumption, only static power consumption. Consider the problem of combinational logic invalid flip-flop in the design, a certain period of time this part of the data is invalid, by enabling the signal to select this part of the logic to hold, to get the effect of avoiding dynamic power consumption.
Prossimo: AMD may fully embrace HBM, CPU and GPU?