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Home > Processor/DSP > Design of Software Phase-locking Based on DSP2812

Design of Software Phase-locking Based on DSP2812

Ora pubblicata: 2020-08-20 09:40:13

Accurately obtaining the phase angle of the fundamental wave and harmonic voltage of the power grid is of great significance in power electronic devices such as inverters and active filters, and usually requires a phase-locked loop to achieve it. Traditional phase-locked loop circuits generally consist of a phase detector, a loop filter, a voltage-controlled oscillator, and a frequency divider. Its working principle is to convert the phase difference between the grid voltage and the internal synchronization signal of the control system into a voltage signal through the phase detector. After filtering by the loop filter, the voltage-controlled oscillator is controlled, thereby changing the frequency and phase of the internal synchronization signal of the system to make it consistent with the grid voltage. Traditional phase-locked loops have problems such as complex hardware circuits, susceptibility to environmental interference, and low phase-locking accuracy. With the development of large-scale integrated circuits and digital signal processors, the use of high-speed DSPs and other programmable devices will The function is realized by software programming. The phase-locked loop control system designed in this paper uses the digital processor TMS320F2812GHHA chip to track and lock the fundamental phase of the power grid and the specific harmonic voltage phase.

DSP

1 design scheme of software phase locked loop

1.1 Work flow

DSP-based software phase-locked loop design The basic idea of this solution is to obtain the synchronization signal by sampling the zero crossing of the voltage, and to use the cycle count of the DSP's internal timer to generate the synchronization signal to achieve the functions of the voltage-controlled oscillator and frequency divider. The period or maximum cycle count value of the timer is used to change the frequency and phase of the synchronization signal. At the same time, the voltage is subjected to A / D conversion and data processing to obtain the phase and frequency of the fundamental wave and harmonic voltage. Adjust the SPWM sine table pointer address. Complete the phase-lock function of the fundamental wave and harmonic voltage.

Generally, the zero-crossing signal can be obtained by detecting the zero-crossing point of any one of the three-phase voltages of the power grid. In Figure 1, the zero-crossing point of the phase A voltage is detected as the zero-crossing signal, and the interrupt generated by the rising edge capture and software filtering is used as the sampling cycle synchronization signal. When the internal clock of the DSP is doubled, the interrupt is captured to the input voltage. When the signal is at the zero crossing point, the pointer that sends the sinusoidal signal is reset to zero to ensure that the reference sinusoidal signal sent by the DSP also crosses zero synchronously when the input voltage signal crosses zero, thereby achieving phase synchronization. This article uses the SPWM trigger mode. The reference sinusoidal signal is a sinusoidal data table that controls the reference point of the inverter output. At the same time, the voltage signal is sampled and analyzed by DSP to perform FFT calculations on its phase and frequency, fundamental wave and harmonics, and the zero-crossing point of phase A voltage. For the phase difference, the frequency of the sine wave at the SPWM output is changed by modifying the timer period register; the phase of the sine wave at the SPWM output is changed by modifying the comparison register, thus completing the phase locking of the fundamental wave and the harmonic voltage.

1.2 Design of Zero Crossing Detection Circuit

The zero-crossing signal has a greater impact on the accuracy of the system phase capture. The system design uses a combination of software and hardware to capture the zero-crossing signal. Obtaining a zero-crossing signal is essentially to provide a synchronization signal to the system, that is, to start A / D conversion every time the signal crosses zero. In this design, the zero-crossing detection circuit collects the zero-crossing point of each phase of the A-phase voltage as the interrupt signal CAP1 generated by the system, so that the interrupt service routine begins to execute.

A pull-up resistor is added to the output of the comparator chip LM339, mainly considering the requirements of the entire circuit for driving, power consumption and speed. The resistors R7 and R8 form a hysteretic comparator. The output signal changes the reference voltage at the non-inverting terminal through the feedback resistor R7 to eliminate the jitter caused by the positive and negative zero crossing of the input signal.

1.3 Software implementation of zero-crossing capture

The zero-crossing detection mainly solves the problem of sampling synchronization. When the detected voltage signal crosses from negative to positive zero, the output of the comparator chip LM339 generates a rising edge. This signal is input to the CAP1 of the DSP2812 event manager EVA pin. Pin CAP1 is preset to trigger an interrupt on the rising edge in the system initialization program. Therefore, when the zero-crossing signal arrives, the CAP1 interrupt subroutine starts to execute, and the TIMER period interrupt of the event manager EVA is turned on. The period is set to T / 128 s ( (Sampling 128 points per cycle), trigger A / D module sampling. Among them, resident T is the interval between the rising edges of the two zero-crossing detection signals captured by CAP1, which is equal to the period T of the signal to be measured in the power grid.

The capture unit CAP of the DSP belongs to the event manager. It can capture the transition of the external pin of the CAP. When a specific transition of the corresponding pin is captured, the corresponding interrupt is triggered and the timer value is stored in a Two levels deep in the FIFO stack. This solution is designed to start data analysis once every 16 points, and throw out a control amount at the same time. This process is an update cycle. The judgment flag ctrl is used to detect whether a new update cycle has been entered to determine whether a new round of data analysis and investment is needed. Out control. The flag dft is used to judge the current data analysis status. When it is 0, it indicates that the data analysis operation is re-initialized. When it is 1, it indicates that the data analysis operation is complete. When it is 2, it indicates that a new round of data analysis is allowed. analysis.

1.4 Software filtering of zero-crossing signals

The interval between the rising edges of the two zero-crossing signals captured by CAP1, that is, the interval between two CAP1 interrupt events, is equal to the period T of the signal to be measured in the power grid. TIMER is continuously counted after the system is initialized, then T is calculated by recording the TIMER count value N between two CAP1 interrupt events in the CAP1 interrupt service routine. At the same time, software filtering is used to determine whether the CAP1 signal is a glitch interference. The process is as follows: The frequency of the fundamental wave of the power grid generally does not exceed 0.2 Hz. When a CAP1 interrupt occurs, the difference between the current and previous counts can be calculated. Less than the power frequency cycle count difference, the captured interrupt is considered to be caused by interference. If the interrupt occurs more than twice in succession, the interrupt returns. At the same time, the number of interrupts generated is accumulated, the pointer position of the sine table at the time of voltage zero crossing is reached when the set range is reached, the pointer address of the sine table is adjusted, and the zero-crossing pointer is calibrated.

1.5 A / D conversion and phase frequency calculation

After the zero-crossing signal is filtered and calibrated by software, when the zero-crossing point of the input voltage signal is captured, the pointer that sends the sinusoidal signal is directly reset to zero to ensure that the reference synchronization zero-crossing of the DSP when the input voltage signal crosses zero, thereby achieving phase synchronization. The phase A voltage zero-crossing signal is sent to pin CAP1 as a reference for a sampling period, and the 128-fold frequency signal of this period is used as a reference for each ADC startup. After the system is initialized, turn on CAP1, and set to start the ADC, the corresponding analog-to-digital conversion, data analysis, and control value input, etc., until it shuts down or fails. Because the system clock frequency of F2812 is very high, which is 150 MHz, the response delay time of the interrupt service routine is very small and can be ignored. In the interrupt service routine of CAP1, the general timer TIMER of the F2812 event manager is set according to the period T of the signal to be measured, and A / D conversion is automatically started for data acquisition every T / 128 s.

The A / D converted signal uses the sliding window FFT algorithm. Based on the sliding window DFT and Pruning-FFT, the DFT is used to select and calculate specific harmonics. According to the characteristics of the fast response of the sliding window and the fast calculation of Pruning-FFT, , So that the processing speed of the DSP reaches the ideal value.

1.6 SPWM Output Phase Frequency Adjustment

The software phase lock output is completed by the capture interrupt and the timer interrupt. The capture interrupt can complete the calculation of the voltage cycle and phase. The timer interrupt is used to output the SPWM waveform. In this solution, the triangle carrier is generated by using the continuous up-down counting mode of the general-purpose timer. When the general-purpose timer is valid, it starts to count up until it equals the value of the period register. Start counting up again and repeat the above process to form a triangular carrier signal. After the triangle wave is obtained, the polarity of the output wave is controlled by the comparison unit to generate a PWM wave.

The TMS320F2812 series DSP has a comparison unit on-chip, which can provide 6 pairs of programmable PWM signals, which provides great convenience for implementing the above algorithm. When the timer has a periodic interrupt, the comparator value needs to be reloaded, that is, the sine value at the moment. Set the carrier ratio to 21 (the carrier ratio should be odd and divisible by 3), that is, the period of a sine wave is equal to the period of 21 carriers, then the phase difference between the two sine waves corresponding to the peaks of two adjacent triangle waves is 360 μ. / 21 = 17.143, and assuming that the sine value of the interruption load in the previous cycle is sin, the sine value of the interruption load in this cycle is sin (z + 17.143).

The initial phase angle of the 5th harmonic is the phase difference between the voltage and the zero-crossing point of phase A voltage calculated by FFT. According to the x and z values, corresponding PWM waves are generated. Because the sine value is often used in real-time calculation, after determining the phase resolution, such as Yiyi, it will cause a large number of repeated calculations. Therefore, the table lookup method is used to pre-store a sine value with a period of 420 points and a phase resolution of 360 yi / 420 = 0.857 yi, because the load value of each comparator is the sine after the previous phase shift of 17.143 yi Value, so just add the address of the last load value to a certain offset, that is, the address of the load value required this time, and the offset is 420/21 = 20. It can be seen that simplifying the sine calculation to read the memory value of the corresponding address will greatly improve the efficiency of the program.

By reading the initial phase angle frequency of the fundamental wave and harmonic voltage in the register and the value of the phase difference from the zero-crossing point, adjust the address of the initial phase angle pointer of the corresponding sine table, and modify the frequency of the sine wave by modifying the timer period register, modify the comparison Registers to change the amplitude and phase of the sine wave, and throw the phase and frequency control at the zero crossing of the next zero-crossing signal to complete the phase lock on the fundamental wave and harmonic voltage and SPWM output.

2 Experimental results and analysis

In a low-voltage active power filtering device, a software phase-locked loop design based on the TMS320F2812 chip as the core controller is used. Experimental results verify that the scheme can well track and lock the fundamental and specific harmonic voltage phases.

(a) Give the synchronous zero-crossing signal waveform, the voltage signal (sine wave) is the phase A voltage, and the zero-crossing signal is a square wave. When the circuit is designed, the amplitude of the voltage sampling signal is converted to 3.3 V, which meets the condition that the zero-crossing signal can be recognized by the pin CAP1.

(b) Give the phase-locked output experiment waveform of the power module. In the figure, waveform 1 is the phase A voltage sampling signal, and waveform 2 is the power module output current waveform. The controller sets the zero crossing of the voltage sampling signal to trigger the synchronous output of the power module. From the experimental results, it can be seen that the phase of the inverter output current of the power module can be synchronized with the zero-crossing point of the sampling signal, and the phase offset is extremely small, achieving the purpose of phase-locking and tracking output of the fundamental wave voltage of the power grid.

(c) Give the experimental waveforms of the phase-locked frequency multiplication output of the power module. In order to facilitate the observation of the effect of phase-locked harmonics, the initial phase angle of the 5th harmonic is set to be in phase with the zero-crossing point of the fundamental wave. The controller sets the zero-crossing point of the sampling signal to follow the voltage, and outputs the 5th-order harmonic current in reverse phase. constant.

The experimental results show that the phase-locked loop of the software can be used to synchronize the inverter output current of the power module and the voltage sampling signal. Adjusting the controller program can track the phase and frequency of the harmonics and lock the grid voltage and specific subharmonic voltage Phase and trace output purpose.

3 Conclusion

This paper presents a technical solution based on DSP2812 to implement software phase-locking of grid voltage. The experimental results show that the scheme can well realize the real-time tracking of the voltage signal period and frequency.

Using software phase-locked loop technology, only the zero-crossing detection and signal adjustment circuits need to be designed, and other functions are completed by the DSP chip, which reduces the problem of external environmental interference and improves the phase-locking accuracy. At the same time, the DSP can modify the software in real time, which can achieve complex control and improve its operability and scalability. With the continuous improvement of DSP performance, its operation speed is getting faster and faster, which will provide more development space for software phase lock technology.

Etichetta: DSP2812

Condividere:

Precedente: Lite-On Technology Selected as a Member of 2012 DJSI two years in a row, ranked as the Sector Leader of Electronic Component & Equipment

Prossimo: Design of S3C2440 processor and Windows CE implementation system

 

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