Hi3519 V101 HD IP Camera Solution

As a new-generation industry-specific SoC designed for the HD IP camera, Hi3519 V101 integrates a newgeneration ISP and uses the latest H.265 video compression encoder in the industry as well as advanced lowpower technology and architecture design. 

These features enable Hi3519 V101 to continuously maintain the leading position in the aspects of low bit rate, high picture quality, and low power consumption. Hi3519 V101 supports 90° or 270° rotation and lens distortion correction by using hardware, which meet requirements in various surveillance application scenarios. It also supports 3A algorithms, which allow customers to design various models of IP cameras that contain integrated camera cores. Hi3519 V101 integrates the POR, RTC, and audio CODEC and supports various sensor levels and clock outputs, which significantly reduces the EBOM cost of the HD IP camera based on Hi3519 V101. The Hi3519 V101 HiSilicon SDK features high stability and ease of use, supports rapid mass production, and facilitates system layout of DVRs, NVRs, and IP cameras.

Hi3519 V101 HD IP Camera Solution diagram

Key Specifications of Hi3519 V101

Processor Core
1.800 MHz A7 core, supporting 32 KB I-cache, 32 KB Dcache, and 128 KB L2 cache
2.1.25G GHz A17 core, supporting 32 KB I-cache, 32 KB D-cache, and 256 KB L2 cache

3.Neon acceleration, integrated FPU

4.ARM@big-LITTLE architecture

Video Encoding

1. H.264 BP/MP/HP
   2.H.265 Main Profile
   3.I/P/B frame, dual-P-frame reference
   4.MJPEG/JPEG baseline encoding
   Video Encoding Performance
   1.Maximum 16-megapixel (4608 x 3456) resolution for H.264/H.265 encoding
   2.Real-time multi-stream H.264/H.265 encoding capability:3840 x 2160@30 fps+1080p@30 fps + 3840 x 2160@2fps snapshot
   3.Maximum JPEG snapshot performance of 3840 x2160@30 fps
   4.CBR, VBR, FIXQP, AVBR, and QPMAP modes
   5.Maximum100 Mbit/s output bit rate
   6.Encoding of eight ROIs 

Key Parts

Hi3519V101

HI3518EV200

Hi3520DV200

Hi3796MV200

Hi3798MV100

Hi3798MV200